JPH0749807Y2 - 光集積回路装置 - Google Patents

光集積回路装置

Info

Publication number
JPH0749807Y2
JPH0749807Y2 JP1987077936U JP7793687U JPH0749807Y2 JP H0749807 Y2 JPH0749807 Y2 JP H0749807Y2 JP 1987077936 U JP1987077936 U JP 1987077936U JP 7793687 U JP7793687 U JP 7793687U JP H0749807 Y2 JPH0749807 Y2 JP H0749807Y2
Authority
JP
Japan
Prior art keywords
integrated circuit
optical integrated
semiconductor substrate
circuit device
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987077936U
Other languages
English (en)
Japanese (ja)
Other versions
JPS63187350U (en]
Inventor
恒幸 林
修 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1987077936U priority Critical patent/JPH0749807Y2/ja
Publication of JPS63187350U publication Critical patent/JPS63187350U/ja
Application granted granted Critical
Publication of JPH0749807Y2 publication Critical patent/JPH0749807Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987077936U 1987-05-23 1987-05-23 光集積回路装置 Expired - Lifetime JPH0749807Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987077936U JPH0749807Y2 (ja) 1987-05-23 1987-05-23 光集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987077936U JPH0749807Y2 (ja) 1987-05-23 1987-05-23 光集積回路装置

Publications (2)

Publication Number Publication Date
JPS63187350U JPS63187350U (en]) 1988-11-30
JPH0749807Y2 true JPH0749807Y2 (ja) 1995-11-13

Family

ID=30926414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987077936U Expired - Lifetime JPH0749807Y2 (ja) 1987-05-23 1987-05-23 光集積回路装置

Country Status (1)

Country Link
JP (1) JPH0749807Y2 (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111334A (ja) * 2007-10-12 2009-05-21 Panasonic Corp 光学デバイスおよびその製造方法、並びに半導体デバイス

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4728448U (en]) * 1971-04-14 1972-12-01

Also Published As

Publication number Publication date
JPS63187350U (en]) 1988-11-30

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